This invention relates generally to address selection circuitry and methods and more particularly to circuitry and methods adapted to provide an address for each one of a plurality of addressable integrated circuits.
As is known in the art, many systems use addressable integrated circuits. One such system is a so-called System Management (SM) bus system and is shown in FIG. 1. Here, the SM bus has two lines; line SDA is for data and addresses and line SCL is for clock pulses. As shown, each one of the addressable Application Specific Integrated Circuits (ASICS) used in the SM system have a single pin ADDR to receive the address to be selected, and stored in, such one of the ASICs. The single pin ADDR allows the designer to tie the pin to one of three signal levels, i.e., a high voltage signal level, a low voltage signal level, or an open circuit, or "floating" voltage signal level. More particularly, each one of the levels corresponds to a different two bit word used in the address of the ASIC. Still more particularly, during an initial address select mode, the signal level on the ADDR pin is converted into one of three possible portions of the address for the ASIC. That is, a slave address register (FIG. 2) is provided in each ASIC. Each register stores, for example, a seven bit address. The five most significant bits are previously stored in the address register. However, the last two bits are derived from the voltage level on the ADDR pin. Thus, here for example, at power-on the level on the ADDR pin is passed through a decoder. Here, for example, if the level on the ADDR pin is high, the decoder produces a two bit word 00. It the level on the ADDR pin is low, the decoder produces a two bit word 11. Finally, if there is an open circuit on the ADDR pin, the decoder produces a two bit word 01. At power-on the two bit word produced by the decoder is stored as the two least significant bits in the slave address register. The contents of the slave address register are then used as the address for the ASIC during the normal mode. That is, during the normal operating mode, the here seven bit address of the ASIC, which is stored in the slave address decoder, is fed to a serial interface (which includes a comparator) of the ASIC. Thus, if the address on the SDA line is the same as the address stored in the address register, comparator indicates to the ASIC that it is the ASIC being addressed.
While such an address select system is useful in some applications if more than three addresses are required additional ADDR pins would be needed for each ASIC to accommodate the three level signal (i.e., a high level voltage, a low level voltage, or an open circuit condition). That is, one of these three conditions would be placed on a corresponding one of the additional ADDR pins of the ASIC.